1. Field of the Invention
The present invention relates to a nonvolatile phase change memory device and to a biasing method for use in a nonvolatile phase change memory device.
2. Description of the Related Art
A phase change memory (PCM) device, also known as Ovonics Unified Memory (OUM) device, includes a memory array formed by a number of memory cells arranged in rows and columns; word lines connecting first terminals of memory cells arranged on the same row; and bit lines connecting second terminals of memory cells arranged on the same column.
Each memory cell is formed by a memory element and a selection element connected in series, wherein the memory element is based on a class of materials which have the property of changing between two phases, namely from an amorphous, disorderly phase and a crystalline or polycrystalline, orderly phase, which have distinct electrical characteristics, namely considerably different values of resistivity. For a detailed description of PCM devices, reference may be made to WO-A-01/45108, U.S. Pat. No. 5,825,046 and GB 1,296,712.
At present, alloys of elements of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, can advantageously be used in phase change memory cells. The currently most promising chalcogenide is formed by a Ge, Sb and Te alloy (Ge2Sb2Te5) and is widely used for storing information in overwritable disks.
In chalcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous phase (more resistive) to the crystalline phase (more conductive) and vice versa.
Individual rows of the memory array are addressed by a row decoder which receives an encoded address and biases the addressed and non-addressed word lines at stable and precise voltages, the values thereof depends upon the operation (read, write, erase, verify) to be performed, while individual columns of the memory array are addressed by a column decoder which receives the encoded address and biases the addressed and non-addressed bit lines at stable and precise voltages, the values thereof depends upon the operation (read, write, erase, verify) to be performed.
Nonvolatile phase change memory devices are typically of a so-called single supply voltage type, namely, they receive from outside a single supply voltage currently having a value of 1.65 V, and voltages having higher values than the external supply voltage and required in the various operations to be performed on the memory cells are generated inside the nonvolatile memory device by one or more voltage elevator circuits, generally known as “voltage boosters” or, more commonly, “charge pumps”. The boosted voltages supplied by charge pumps are, however, generally far from stable, and consequently are regulated and stabilized by voltage regulators.
In particular, PCM cells require relatively high single bit writing currents, and therefore during writing the addressed bit line is generally biased at relatively high writing voltage, e.g., about 6V the addressed word line is generally biased at a reference voltage, e.g., about 0V, the non-addressed word lines are biased at a first biasing voltage lower than the writing voltage, e.g., equal to two thirds of the writing voltage, i.e., about 4V, and the non-addressed bit lines are biased at a second biasing voltage also lower than the writing voltage, e.g., equal to one third of the writing voltage, i.e., about 2V
During reading, instead, the addressed bit line is biased at a reading voltage generally lower than the writing voltage, e.g., about 4V, the addressed word line is biased at the reference voltage, i.e., about 0V, and the non-addressed word and bit lines are biased at the same biasing voltage lower than the reading voltage, e.g., equal to half of the reading voltage, i.e., about 2V.
In the example considered, voltage drop across an addressed PCM cell (i.e., on the series of the memory element and the selection element) is about 6V during writing and about 4V during reading, whereas voltage drop across a non-addressed PCM cell is about 2V during writing and about 0V during reading, not including voltage drops across parasitic resistances of word and bit lines, across output resistances of voltage regulators, and across pass transistors of row and column decoders. Such parasitic voltage drops may range, as a whole, between 0.5V and 1V during writing and are practically negligible during reading.
Use of the aforementioned biasing voltages has negative repercussions both on area occupation of row and column decoders and on power consumption of charge pumps and memory array.
In fact, the use of the aforementioned biasing voltages causes prior art devices to use of medium voltage transistors with a gate oxide thickness of about 12 nm and a minimum channel length of 0.5 μm, and this implies a large area occupation on silicon both for row and column decoders.
Furthermore, the aforementioned biasing voltages generate relatively high leakage currents in the non-addressed memory cells, the sustenance of which implies a non-negligible power consumption due to parasitic dissipation of charge pumps, wirings, etc.